1. Field of the Invention
The present invention generally relates to the simulation of logic circuits and more particular to a specific logic circuit for verifying the suitability of models used for logic simulations.
2. Discussion of the Related Art
FIG. 1 symbolizes a logic cell which may be an elementary logic circuit or a standard cell element. Generally, the cell comprises one or several inputs A.sub.0, A.sub.1 . . . A.sub.n, and at least one output Z. Each path between an input and an output is hereinafter called an "arc".
Such a cell, taken alone, may be analyzed by an analog simulator, such as SPICE, which takes into account the lowest structure level (the transistors) of the cell. The results of the simulation allow all the characteristic parameters of the cell to be acquired, especially the propagation time tp of each arc. A propagation time is the time taken by an edge of a signal applied to the corresponding input A to appear on the output Z, with the same polarity or not.
For a given arc, several propagation times exist. Indeed, a propagation time depends on the polarity or direction of the edge presented at the input and also depends on the states present on the other inputs. Thus, for a single arc, the number of different propagation times is equal to the sum of the number of combinations of the states of the other inputs which sensitize the studied input to positive edges and of the number of combinations of the states of the other inputs which sensitize the studied input to negative edges. An input is so called "sensitized" when an edge applied to this input effectively causes an edge on the output of the cell.
The propagation times of each arc may be found through an analog simulation by using suitable stimulations derived from the logic function of the cell. The accuracy of the results depends on the accuracy of the transistor models used by the simulator. The transistor models involve parameters which depend on the technology to simulate.
Refining the parameters of the models of an analog simulator is achieved throughout the maturation period of a technology. At the birth of a technology, the parameters are unknown and roughly estimated, which does not provide satisfactory results. Refining of the parameters is achieved by comparing numerous measurement results to simulation results.
In practice, a logic circuit may be constructed from several thousand standard cells. It is then not reasonable to simulate the entire logic circuit with an analog simulator, because this would take too much time. One then uses a logic simulation, allowed in particular by functional simulation languages, such as VHDL or VERILOG.
A logic simulation takes into account the logic functions of the cells and precomputed propagation times. Default values for the propagation times tp may be provided by an analog simulation of the cells. These default values are generally corrected in a back-annotation process from the values computed by a delay calculator which takes into account the silicon layout of the simulated circuit (i.e. the effective capacitances of the interconnections after routing).
However, it is not possible to use all the propagation times of each arc of each cell, because the simulation would then again take too much time and would need an enormous data base.
A common way to proceed is to use the worst case situation, i.e. one uses the highest propagation time for each arc and for each edge polarity.
With this solution, the real circuit will always be faster than what the simulation indicates. In fact, in many cases, the simulation will invalidate the circuit although it would operate conveniently in reality.
A better way to proceed would be to organize, for each arc and each edge polarity, the propagation times in several classes, the criterion for grouping the propagation times in a class being to have a maximum distance between propagation times which is smaller than a given threshold.
Then, one would use the highest propagation time in each class, the class used being determined by a corresponding set of conditions on the states of the inputs of the cell.
However, the conditions which determine a class are often complex and passing classes through a temporal model of a cell raises problems, because most of the design tools do not support this type of modeling (delay calculator, back-annotation, simulation with conditional delays . . . ).
In practice, this solution is not exploited. There are therefore two distinct problems. The first relates to an exhaustive characterization of a cell in order to deduce an acceptable temporal model. The second problem is the validation of the chosen temporal models and their use by design tools (delay calculator, logic simulator with back-annotated delays . . . ) in the context of a design methodology such as it is applied by the user.